MCS-284 schedule (Fall 2006)

A single number in the reading column means to read that entire chapter. When a reading is indicated as going to a particular page number, it means up to the first heading on that page. The same section number on the next class day then indicates to finish the section.

This is my best guess as to the rate at which we will cover material. However, don't be shocked if I have to revise this schedule as the course progresses.
Date
9/6 Introduction (class instead of lab)
9/7 1Computer abstractions and technology
9/8 2.1-2.6Instructions

9/11 2.7-2.8Procedures and strings in assemblyProcessor proposal
9/12 2.9-2.11More on assembly programming, intro to xspim
9/13 Lab 0: Under the hood
9/14 2.13,2.15Assembly programming examples
9/15 CD: A.1-A.6,A.9Lab 1: Elementary assembly programming

9/18 2.16-2.18Yet more on assembly languageProcessor assignment
9/19 3.1-3.3Two's complement, addition, and subtraction
9/20 Lab 1 (continued)
9/21 3.4-3.5Multiplication and division
9/22 3.6Floating point arithmeticLab 1

9/25 Lab 2: More advanced assembly programming
9/26 B.1-B.3Combinatorial LogicBen
9/27 Lab 2 (continued)
9/28 B.7-B.11Sequential logicAdam, Justin
9/29 More on Sequential logicJosh, John, Alex

10/2 Yom Kippurno class
10/3 Nobel Conference
10/4 Nobel Conference
10/5 Chapter 4Performance
10/6 Milo Martin

10/9 articleMore on performance
10/10Review; catch-upHW chapters 1-4, A, B
10/11Lab 2 (continued)
10/12Exam 1
10/13

10/165.1-5.3A simple datapath
10/175.4-p.329A single-cycle processor
10/18Lab 2 (continued)
10/195.4More on the single-cycle processor
10/205.5A multiple-cycle processor

10/23Reading day
10/24Reading day
10/25Lab 2 (continued)
10/26More on the multiple-cycle processor
10/275.6, CD 5.7Microprogramming; exceptions

10/306.1Pipelining
10/316.2A pipelined datapth
11/1 Lab
11/2 6.3Pipelined controlLab 2
11/3 6.4Forwarding and lab 3 preview

11/6 6.5Stalls
11/7 6.6Branches
11/8 Lab 3: Measuring processor architectures' performance
11/96.8-6.12Superscalar and advanced pipelining
11/10Review; catch-upHW chaps. 5-6

11/13Intra-term test 2
11/147.1-7.2Caches
11/15Lab 3 (continued)
11/167.3Cache performance
11/17Lab 3 (continued)

11/20Lab 3 (concludes)
11/217.4Virtual memoryLab 3
11/22(no class)
11/23Thanksgiving
11/24Thanksgiving

11/27Lab 4: Cache simulation
11/287.5Memory hierarchies
11/29Lab 4 (continued)
11/30Lab 4 (continued)
12/1 Lab 4 (continued)

12/4 Lab 4 (continued)
12/5 8.1-8.3Input/output devices
12/6 8.4-8.5Class presentations
12/7 Lab 4 (concludes)
12/8 9.1-9.3Bus-based MIMD architectures

12/119.4-9.6Network-based MIMD architecturesLab 4
12/129.7-9.10More on multiprocessors
12/13Review; catch-up; evaluationHW chaps. 7-9

12/18Final3:30-5:30pm