MCS-284 schedule (Fall 2006)

A single number in the reading column means to read that entire chapter. When a reading is indicated as going to a particular page number, it means up to the first heading on that page. The same section number on the next class day then indicates to finish the section.

This is my best guess as to the rate at which we will cover material. However, don't be shocked if I have to revise this schedule as the course progresses.

Date
9/6 Introduction (class instead of lab)
9/7 1 Computer abstractions and technology
9/8 2.1-2.6 Instructions

9/11 2.7-2.8 Procedures and strings in assembly Processor proposal
9/12 2.9-2.11 More on assembly programming, intro to xspim
9/13 Lab 0: Under the hood
9/14 2.13,2.15 Assembly programming examples
9/15 CD: A.1-A.6,A.9 Lab 1: Elementary assembly programming

9/18 2.16-2.18 Yet more on assembly language Processor assignment
9/19 3.1-3.3 Two's complement, addition, and subtraction
9/20 Lab 1 (continued)
9/21 3.4-3.5 Multiplication and division
9/22 3.6 Floating point arithmetic Lab 1

9/25 Lab 2: More advanced assembly programming
9/26 B.1-B.3 Combinatorial Logic Ben
9/27 Lab 2 (continued)
9/28 B.7-B.11 Sequential logic Adam, Justin
9/29 More on Sequential logic Josh, John, Alex

10/2 Yom Kippur no class
10/3 Nobel Conference
10/4 Nobel Conference
10/5 Chapter 4 Performance
10/6 Milo Martin

10/9 article More on performance
10/10 Review; catch-up HW chapters 1-4, A, B
10/11 Lab 2 (continued)
10/12 Exam 1
10/13

10/16 5.1-5.3 A simple datapath
10/17 5.4-p.329 A single-cycle processor
10/18 Lab 2 (continued)
10/19 5.4 More on the single-cycle processor
10/20 5.5 A multiple-cycle processor

10/23 Reading day
10/24 Reading day
10/25 Lab 2 (continued)
10/26 More on the multiple-cycle processor
10/27 5.6, CD 5.7 Microprogramming; exceptions

10/30 6.1 Pipelining
10/31 6.2 A pipelined datapth
11/1 Lab
11/2 6.3 Pipelined control Lab 2
11/3 6.4 Forwarding and lab 3 preview

11/6 6.5 Stalls
11/7 6.6 Branches
11/8 Lab 3: Measuring processor architectures' performance
11/9 6.8-6.12 Superscalar and advanced pipelining
11/10 Review; catch-up HW chaps. 5-6

11/13 Intra-term test 2
11/14 7.1-7.2 Caches
11/15 Lab 3 (continued)
11/16 7.3 Cache performance
11/17 Lab 3 (continued)

11/20 Lab 3 (concludes)
11/21 7.4 Virtual memory Lab 3
11/22 (no class)
11/23 Thanksgiving
11/24 Thanksgiving

11/27 Lab 4: Cache simulation
11/28 7.5 Memory hierarchies
11/29 Lab 4 (continued)
11/30 Lab 4 (continued)
12/1 Lab 4 (continued)

12/4 Lab 4 (continued)
12/5 8.1-8.3 Input/output devices
12/6 8.4-8.5 Class presentations
12/7 Lab 4 (concludes)
12/8 9.1-9.3 Bus-based MIMD architectures

12/11 9.4-9.6 Network-based MIMD architectures Lab 4
12/12 9.7-9.10 More on multiprocessors
12/13 Review; catch-up; evaluation HW chaps. 7-9

12/18 Final 3:30-5:30pm

Date
9/6		Introduction (class instead of lab)
9/7	1	Computer abstractions and technology
9/8	2.1-2.6	Instructions

9/11	2.7-2.8	Procedures and strings in assembly	Processor proposal
9/12	2.9-2.11	More on assembly programming, intro to xspim
9/13		Lab 0: Under the hood
9/14	2.13,2.15	Assembly programming examples
9/15	CD: A.1-A.6,A.9	Lab 1: Elementary assembly programming

9/18	2.16-2.18	Yet more on assembly language	Processor assignment
9/19	3.1-3.3	Two's complement, addition, and subtraction
9/20		Lab 1 (continued)
9/21	3.4-3.5	Multiplication and division
9/22	3.6	Floating point arithmetic	Lab 1

9/25		Lab 2: More advanced assembly programming
9/26	B.1-B.3	Combinatorial Logic	Ben
9/27		Lab 2 (continued)
9/28	B.7-B.11	Sequential logic	Adam, Justin
9/29		More on Sequential logic	Josh, John, Alex

10/2	Yom Kippur	no class
10/3	Nobel Conference
10/4	Nobel Conference
10/5	Chapter 4	Performance
10/6		Milo Martin

10/9	article	More on performance
10/10		Review; catch-up	HW chapters 1-4, A, B
10/11		Lab 2 (continued)
10/12		Exam 1
10/13

10/16	5.1-5.3	A simple datapath
10/17	5.4-p.329	A single-cycle processor
10/18		Lab 2 (continued)
10/19	5.4	More on the single-cycle processor
10/20	5.5	A multiple-cycle processor

10/23	Reading day
10/24	Reading day
10/25		Lab 2 (continued)
10/26		More on the multiple-cycle processor
10/27	5.6, CD 5.7	Microprogramming; exceptions

10/30	6.1	Pipelining
10/31	6.2	A pipelined datapth
11/1	Lab
11/2	6.3	Pipelined control	Lab 2
11/3	6.4	Forwarding and lab 3 preview

11/6	6.5	Stalls
11/7	6.6	Branches
11/8		Lab 3: Measuring processor architectures' performance
11/9	6.8-6.12	Superscalar and advanced pipelining
11/10		Review; catch-up	HW chaps. 5-6

11/13		Intra-term test 2
11/14	7.1-7.2	Caches
11/15		Lab 3 (continued)
11/16	7.3	Cache performance
11/17		Lab 3 (continued)

11/20		Lab 3 (concludes)
11/21	7.4	Virtual memory	Lab 3
11/22	(no class)
11/23	Thanksgiving
11/24	Thanksgiving

11/27		Lab 4: Cache simulation
11/28	7.5	Memory hierarchies
11/29		Lab 4 (continued)
11/30		Lab 4 (continued)
12/1		Lab 4 (continued)

12/4		Lab 4 (continued)
12/5	8.1-8.3	Input/output devices
12/6	8.4-8.5	Class presentations
12/7		Lab 4 (concludes)
12/8	9.1-9.3	Bus-based MIMD architectures

12/11	9.4-9.6	Network-based MIMD architectures	Lab 4
12/12	9.7-9.10	More on multiprocessors
12/13		Review; catch-up; evaluation	HW chaps. 7-9

12/18	Final	3:30-5:30pm